User manual

New to GateLab or exploring its digital logic design pipeline? Follow this 4-step tutorial demonstrating how algebraic derivation connects directly to 74xx breadboard construction and $2^n$ verification.

The whole product is one loop, and it is worth doing once end to end before anything else:

1. In Theory, write a function — say F(A,B,C) = A'B + BC. It is minimized as you type.
2. Open the Build it tab in Theory (or navigate to /build) and press Build this circuit in the lab. Real 74xx chips appear, wired, with the power rails already connected.
3. In the Lab, open Verify. It sweeps all 2ⁿ input combinations through the circuit and diffs the result against your algebra.
4. Now break it on purpose — pull the wire off pin 14 — and watch the lab tell you exactly what you did.

You never have to go through Theory, though. The lab has its own From equation button, and you can wire a circuit up from nothing and verify it against a target you type in later.

Everything lands on the same function, whichever way you write it. The parser accepts all of the usual notations, so you can type what your textbook uses:

Juxtaposition is AND, so AB is A AND B. An apostrophe is NOT, so A' is NOT A.

Type an expression at the top, or click outputs in the truth table or K-map. Every view updates as you type:

• Truth table— click any output bit to cycle it through 0, 1 and X (don't care).
• K-map — rendered with the prime implicants looped. The loops are not re-derived for the drawing; they are the Quine–McCluskey result, drawn.
• Derivation — Quine–McCluskey step by step: grouping by number of 1s, matching terms that differ by one bit, and the prime implicant chart that picks the essential ones.
• Canonical forms — minterm list (Σm), maxterm list (ΠM), and the numeric vectors.

“Implement this using NAND only” is not a suggestion — in a digital logic course it is the whole exercise. So the rule is chosen before you build:

When a rule is active, the palette narrows to match — you cannot place gates you are not allowed to use — and the synthesizer is steered by it, so Build this circuit obeys the rule rather than apologizing for breaking it.

The power rails matter here. A constant 1 is not 0-preserving, so having +5V on the board makes {XOR, AND} universal when it would otherwise be useless.

Diagramis a canvas. Drag a block out of the palette, drag from one of its pins to another block's pin to wire them, and drag the blocks around until it reads the way you want.

• Drag a pin to a pin to wire them. Click a wire to select it.
• Drag empty space to marquee-select. Hold ⌥ or drag with the middle button to pan; ⌘-scroll to zoom.
• R rotates the selection a quarter turn, ⇧R the other way.
• Arrow keys nudge one grid step, ⇧ and an arrow one pixel. Hold ⌘ while dragging to ignore the grid entirely.
• ⌘Z / ⇧⌘Z undo and redo. ⌘D duplicates. ⌫ deletes.
• Arrange tidies everything into left-to-right dataflow, and the result is still yours to move.

Getting the wires straight

A pin sits at a fraction of its block's height, and two different parts almost never line up — so a rough drag used to leave a small two-bend jog in the middle of a wire that plainly wanted to be straight. While you are dragging, a block within a few pixels of straightening one of its wires is now pulled the rest of the way, and a whole bus of them agrees on one shift.

Building bigger things

Select several blocks and press G. They fold into one block, which joins the palette and can be placed as many times as you like. Build a 4-bit adder once, group it, place it four times — that is a 16-bit adder, and it is how every real digital system is put together.

Exporting

SVG first, and deliberately. It is a vector, it stays sharp at any size, Word and Google Docs both accept it, and you can open it afterwards to add an annotation the tool did not think of. PNG is there at 1×, 2× and 4× for submission portals that refuse anything else, and File → Save as JSON keeps the editable document.

LaTeX is there for reports written in LaTeX, where a PNG of a circuit has the wrong fonts, the wrong line weights and goes soft in print. It writes a TikZ picture of the same drawing — download a standalone .tex you can compile on its own, or copy the figure straight into your document.

Drag parts from the palette. Click one pin, then another, to wire them — the wire routes itself around obstacles. Click a switch to toggle it.

Logic is four-state: 0, 1, Z and X. Z is a floating, undriven net — not zero. X is a conflict or power-up indeterminate state. This is the difference between a simulator that tells you your circuit works and one that tells you the truth: a boolean simulator reads an unconnected input as false and stays quiet.

Wires are colored by net, cycling through eight hues, for the same reason real jumper wire is multicolored — so you can trace one. But Z and X keep their own unmistakable color and dashing. A broken wire must never be able to look like a working one.

The Presets menu is organized around one idea: complex circuits are built from simple ones.

• Building blocks — half and full adders, comparators, multiplexers, decoders, priority encoders.
• Hierarchical blocks — full adders wired from two half adders and an OR; 4:1 mux as a tree of three 2:1 muxes; 8:1 mux from two 4:1s and a 2:1.
• Large circuits — 2-, 4-, 8- and 16-bit ripple-carry adders. Watch the top sum bit wait for the carry to walk all the way up.

The seven gates, what each one means, and the algebraic properties that decide how it behaves when you build with it.

The GateLab 74xx TTL integrated circuit catalog covers 17 standard DIP packages, transcribed directly from official Texas Instruments datasheets.

Switching from Schematic to Breadboard seats your components onto the MODEL 74XX-TTL · 5V BENCH Digital Logic Trainer, a high-fidelity virtual workbench with integrated power, pulsing, input switches, and logic indicators.

Combinational outputs depend solely on current inputs. Flip-flops introduce memory: their outputs change only at clock edges.

The Faults panel runs as a separate pass from value resolution. The simulator always produces a value so the board stays usable; the fault panel separately alerts you to real physical wiring errors:

The Verification Bridge sweeps all $2^n$ input combinations through your wired circuit and diffs the results against your algebraic Boolean specification.

• Variable-Label Alignment: Input switches match Boolean variables by exact label name (e.g. A, B, C or S, D0, D1), not array order, supporting up to 16 variables.
• Tarjan SCC Feedback Detection:Netlists are checked with Tarjan's Strongly Connected Components algorithm; any combinational feedback loops or unclocked latches are caught and flagged as non-combinational memory.
• 5 Automated Fault Hypotheses: When verification fails, GateLab tests root-cause hypotheses:
  • UNPOWERED_IC: IC supply pins missing +5V or GND.
  • FLOATING_INPUT: Gate inputs disconnected and drifting to X.
  • output-inverted: Circuit output is the exact complement of target (e.g. NAND used for AND).
  • output-stuck: Circuit output is permanently stuck at 0 or 1.
  • inputs-swapped: Tests if swapping any two input signals (e.g. A ↔ B) produces a 100% match.

The GateLab Timing Drawer houses a Dual Timing Engine designed for both combinational hazard analysis and sequential clock debugging:

Remember: minimal is not hazard-free. The redundant consensus term that Quine–McCluskey discards during minimization is precisely the term that prevents a static-1 glitch. Add it back to eliminate the spike!

Report assembles the whole derivation into one printable page: truth table, K-map, tabular reduction, schematic/breadboard snapshot, and the row-by-row verification matrix.

Print it with your browser (⌘P / Ctrl-P) and “Save as PDF”. It outputs vector SVG elements so figures stay crisp and publication-ready.

GateLab runs 100% in your browser. All designs and states are saved locally in localStorage with zero server uploads.

Found a wrong answer, a bad pinout, or something that should exist and does not? That is the most useful thing you can send.