Digital Logic Lab Report
F(A, B, C, D) = Σm(0, 1, 2, 5, 6, 7, 8, 9, 10, 14)
1.The function
- As entered
F(A,B,C,D) = Σm(0,1,2,5,6,7,8,9,10,14)- Variables
A, B, C, D (4 → 16 rows)- Canonical SOP
- 40 literals
- Minimal SOP
B'·C' + C·D' + A'·B·D— 7 literals (33 fewer)
2.Truth table and Karnaugh map
B'C'4 cells · A, D cancel out · wrapsCD'4 cells · A, B cancel outA'BD2 cells · C cancel out
The loops are not drawn by a second algorithm — they are the prime implicants found below, rendered onto the grid.
3.Quine–McCluskey reduction
Column 1 — group the minterms by number of 1s
0 ones
00000
1 one
00011
00102
10008
2 ones
01015
01106
10019
101010
3 ones
01117
111014
Column 2 — combine terms differing in one bit
0 ones
000-0, 1
00-00, 2
-0000, 8
1 one
0-011, 5✓
-0011, 9
0-102, 6
-0102, 10
100-8, 9
10-08, 10
2 ones
01-15, 7✓
011-6, 7✓
-1106, 14
1-1010, 14
Column 3 — combine terms differing in one bit
0 ones
-00-0, 1, 8, 9✓
-0-00, 2, 8, 10✓
1 one
--102, 6, 10, 14✓
Prime implicant chart
| 0 | 1 | 2 | 5 | 6 | 7 | 8 | 9 | 10 | 14 | |
|---|---|---|---|---|---|---|---|---|---|---|
| A'C'D | · | × | · | × | · | · | · | · | · | · |
| A'BD | · | · | · | × | · | × | · | · | · | · |
| A'BC | · | · | · | · | × | × | · | · | · | · |
| B'C'★ | × | × | · | · | · | · | × | × | · | · |
| B'D' | × | · | × | · | · | · | × | · | × | · |
| CD'★ | · | · | × | · | × | · | · | · | × | × |
★ = essential: the only implicant covering some minterm, so every cover must include it.
4.Implementation
Gate-family comparison
- Mixed gates: 3 ICs (7404, 7408, 7432), 10 gatesfewest chips
- NAND-only: 3 ICs (3x 7400), 12 gates
- NOR-only: 3 ICs (3x 7402), 12 gates
No circuit has been built yet in the Lab
Synthesize or wire a circuit on schematic or breadboard to embed circuit drawings, pin connections, and bill-of-materials in this report.
5.Verification
Verification requires a built circuit
Once a circuit is built in the Lab, the automated verification bridge sweeps every row of the truth table and compares live simulation against the derived algebra.